1. Field of Invention
The present invention relates to a method of manufacturing flash memory. More particularly, the present invention relates to a split-gate flash memory structure and a corresponding manufacturing method.
2. Description of Related Art
Flash memory is a type of memory that permits multiple read/write and erase operations. Since stored data is preserved even if power to the device is cut off, flash memory is widely used as a non-volatile memory device in personal computers and electronic equipment.
A typical flash memory unit has doped polysilicon layers to function as floating gate and control gate and a substrate. The floating gate and the control gate are separated from each other by a dielectric layer. Meanwhile, the floating gate and the substrate are separated from each other by a tunnel oxide layer. To write/erase data, a bias voltage is applied to the control gate and the source/drain region so that electrons are injected into the floating gate or the electrons are pulled out from the floating gate. To read data off the flash memory, an operating voltage is applied to the control gate so that the charge-up state of the floating gate will affect the on/off state of the underlying channel. The on/off status of the channel determines the read-out to be a logic level ‘1’ or ‘0’.
To erase data from the flash memory, the substrate, the drain (source) terminal or the control gate is at a relatively high potential. Tunneling effect is utilized so that electrons penetrate through a tunnel oxide layer to the substrate or drain (source) terminal (that is, the substrate erase or drain (source) side erase) or pass through the dielectric layer into the control gate. However, in erasing data inside the flash memory, the quantity of electrons bled out of the floating gate during a flash memory erasing operation is difficult to control. Ultimately, too many electrons may bleed out from the floating gate leading to a state often referred to as over-erasure. Severe over-erasure may result in a conductive channel forming underneath the floating gate even without the application of an operating voltage and hence lead to erroneous readout data. To reduce the over-erase problem, most flash memory deploys a split-gate design. A major aspect of a split-gate flash memory is that, aside from the portion over the floating gate, a portion of the control gate is lying over the substrate with a gate dielectric layer formed between the two layers. With this arrangement, a conductive channel is prevented from forming underneath the control gate so that the source/drain regions remain nonconductive and data read-out errors are minimized. However, the each split-gate unit occupies a memory cell area larger than a conventional erasable programmable read-only-memory with tunnel oxide (ETOX). Hence, the flash memory has an overall level of integration slightly below other types of memory design.